The methodology of programming programmable memories, such as proms, eproms, eeproms, and flash memories, has changed through the years. In the beginning programmable memories were programmed in a special apparatus, a prom programmer, before the programmable memory was mounted on a circuit board it was meant to operate on. During approximately the same time period, circuit boards were first tested as to their electrical copper tracks, and then after all components had been mounted, their functionality was tested by placing the circuit boards in different test jigs. This type of testing, referred to as in-circuit tests, where components were contacted via bed-of-nail fixtures, has become more and more difficult to realize due to increased complexity. This prompted a replacement of physical contacting via nails with design-integrated pin electronics, electronic nails. An IC's functional core logic is isolated by having scan cells integrated directly on the silicon boundary, functionally commonly between the IC's functional core logic and the IC's physical pins. Scan cells can thus either be transparent, i.e. functionally removed, or intercept outgoing and incoming signals to and from physical pins or the core logic. Further, the scan cells are serially coupled together in a scan cell chain. Scan cells are available in various types, such as capture cells for measurements only and universal cells for measurements and stimulation, and comprises a number of clocked latches.
The scan cells' line interconnection, the scan cell chain, allows test vectors to be serially shifted on to the IC's physical pins as well as allowing scanning and shifting out of externally applied information. Standard IEEE 1149.1 defines a uniform, chip-internal test control logic as well as a standardized bus interface, a testbus. The testbus only needs four lines, with an optional fifth reset line, for complete control. Using this boundary scan architecture, manufacturing faults such as opens, shorts and misplacements are easily detected and localized. The potential of the boundary scan architecture has expanded its fields of application to also include in-system programming of programmable memory devices. A circuit board can thus be manufactured with all components mounted, including programmable memories, and then be tested and programmed for use. Which means that first when a circuit board has to be delivered, its programmable memories are programmed with the latest upgraded software.
Unfortunately as memory sizes increase so does the programming time. Attempts have been made to come to grips with these ever-increasing programming times, for example by increasing the serial clock rate of the boundary scanning. This method of decreasing the programming times is unfortunately heavily dependent on the boundary scan components and their maximum clock rate, and the boundary scan test system's maximum clock rate. There is still room for improvement on how to decrease programming times in a boundary scan environment.